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Unit 222 Periods Allocated

Introduction to Computer Architecture

Explores the evolution of computing devices, processor execution mechanics, and computer hardware architectures.

Syllabus Competency Mappings

Level 2.1Competency Level

Elicits the significant changes occurred in the computers from generation to generation.

Key Topics:
  • Early calculating aids (mechanical, electromechanical)
  • Generations of computers (1G to 4G and future)
Level 2.3Competency Level

Explores the Von Neumann Architecture.

Key Topics:
  • Stored program control concept
  • Components: ALU, CU, Memory, Registers, Buses (Address, Data, Control)
  • Fetch-Execute cycle

A/L ICT Competency Study Guide

1. The Von Neumann Architecture

Proposed in 1945, the Von Neumann Architecture is the foundation of almost all modern general-purpose computers. It introduces the Stored Program Concept, which dictates that both program instructions and data are stored in the same read-write memory (RAM).

The architecture consists of three main components:

  1. Central Processing Unit (CPU): The brain containing logic and registers.
  2. Main Memory (RAM): Holds the active instructions and data.
  3. Input/Output Interfaces: Interconnects with external peripherals.

2. Inner Structure of the CPU

  • Arithmetic Logic Unit (ALU): Performs mathematical (+, -, *, /) and logical comparisons (AND, OR, NOT).
  • Control Unit (CU): Directs data flow inside the CPU, generates clock synchronization pulses, and coordinates the fetch-execute cycle.
  • Registers (High-speed Storage):
    • Program Counter (PC): Stores the memory address of the next instruction to be fetched.
    • Memory Address Register (MAR): Holds the memory address currently being read from or written to.
    • Memory Data Register (MDR): Holds the actual instruction or data fetched from or written to memory.
    • Accumulator (ACC): Stores the temporary intermediate results of the ALU operations.

3. System Buses

Buses are parallel electrical lines used for communication between the CPU and memory:

  • Address Bus (Unidirectional): Carries the memory address being accessed from the CPU to memory.
  • Data Bus (Bidirectional): Transfers the actual instructions/data between CPU and memory/IO.
  • Control Bus (Bidirectional): Carries control signals (e.g., Memory Read, Memory Write) from the CU.

4. The Fetch-Execute Cycle

The CPU repeatedly performs three core operations:

  1. Fetch: The CPU copies the address from the PC to the MAR. The instruction stored at that address in RAM is read via the Data Bus into the MDR. The PC is then incremented by 1 to point to the next instruction.
  2. Decode: The Control Unit reads and decodes the instruction in the Current Instruction Register (CIR) to determine what operation to perform.
  3. Execute: The CPU carries out the instruction (e.g., loading data, performing an ALU math sum, storing a result).

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